An IEEE 1149.1 compliant test control architecture

This paper deals with a design methodology and associated architecture to s upport the control of on-chip DFT and BIST hardware. The work is general in that it supports numerous test methods, such as partial and full scan, mul tiple and reconfigurable scan chains, and both test per clock BIST and scan BIST. The results presented here are compatible with the IEEE 1149.1 bound ary scan architecture. The work is based on a hierarchical control methodol ogy that includes systems, PCBs and MCMs. Various options for assigning con trol functions to be on-chip or off-chip are described. A new partially dis tributed test control architecture is introduced that includes an internal test bus and distributed local controllers. There are three main modes of c ontrol of test resources, namely local static control, dynamic control and global static control. We show how the control mechanism can be implemented together with the IEEE 1149.1 test protocol. The synthesis of the on-chip test control hardware has been automated in a system called CONSYST.