Design methodology for a DVB satellite receiver ASIC

This contribution describes design methodology and implementation of a sing le-chip timing and carrier synchronizer and channel decoder for digital vid eo broadcasting over satellite (DVB-S). The device consists of an A/D conve rter with AGC, timing and carrier synchronizer with matched filter, Viterbi decoder including node synchronization, byte and frame synchronizer, convo lutional de-interleaver, Reed Solomon decoder, and a descrambler. The system was designed in accordance with the DVB specifications. It is ab le to perform Viterbi decoding at data rates up to 56 Mbit/s and to sample the analog input values with up to 88 MHz. The chip allows automatic acquis ition of the convolutional code rate and the position of the puncturing mas k. The symbol synchronization is performed fully digitally by means of inte rpolation and controlled decimation. Hence, no external analog clock recove ry circuit is needed. For algorithm design, system performance evaluation, co-verification of the building blocks, and functional hardware verification an advanced design m ethodology and the corresponding tool framework are presented which guarant ee both short design time and highly reliable results. The chip has been fa bricated in a 0.5 mu m CMOS technology with three metal layers. A die photo graph is included.