Automatic VHDL-C interface generation for distributed cosimulation: Application to large design examples

For functional validation of heterogeneous embedded systems, hardware/softw are (Hw/Sw) cosimulation methodology is mandatory. This paper deals with a distributed cosimulation environment for heterogeneous systems prototyping. The cosimulation environment allows handling all kinds of distributed arch itectures regardless the communication scheme used, cosimulation at differe nt levels of abstraction and smooth transition to the cosynthesis process. The approach can handle any number of hardware modules, software modules, a nd debugging tools, which can be used simultaneously. This flexibility is o btained thanks to an automatic cosimulation interface generation tool, whic h creates links between Hw and Sw simulation environments. The resulting en vironment is very easy to use and our cosimulation model has been validated on very large industrial tramples. The experiments show that VHDL-C cosimu lation is faster than classical simulation approaches.