Size-configurable 200-MHz low-power SRAM macrocells for MPEG2 video-encoding LSIs: Performance enhancement with embedded registers

High-performance SRAM macrocells used in the MPEG2 video-encoding LSI chip sets are described. In designing 13 kinds of SRAMs with different sizes, si ze-configurable memory architecture is employed to shorten design turnaroun d time. Input and output registers are embedded in the SRAMs for reducing o utput delay and the timing margin in the presence of skews between input si gnals. The increase of access time in the read cycle following a writing cy cle is suppressed by avoiding overcharging bitlines during the writing-reco very time. In order to reduce recovery time and power dissipation, sense am plifiers and wordlines are inactivated during the writing-recovery time. A redundant address-decoding scheme is also proposed to reduce the number of unnecessarily activated memory cells when a wordline is selected. A 4K-word x 24-bit SRAM test chip is fabricated with a 0.5-mu m CMOS process. The ch ip demonstrates 200-MHz operation under 3.3-V, 25 degrees C typical conditi ons and achieves low power dissipation of 110 mW at the 81-MHz operating fr equency used in the MPEG2 video-encoding LSI chip sets. (C) 1999 Scripta Te chnica.