The formation of Ti-polycide gate structure with high thermal stability using chemical-mechanical polishing (CMP) planarization technology

A planarized Ti-polycide gate structure with high thermal stability has bee n developed using a chemical-mechanical polishing (CMP) process for the app lication of high-speed DRAM devices. For a given gate length and without an y thermal annealing, the planarized Ti-polycide structure developed via a n ovel gate line formation technology manifested a substantially lower gate l ine resistance than that produced by a conventional processing method. In a ddition, the agglomeration of the TiSi2 gate in a deep submicron regime was suppressed even after high-temperature cycling at 850 degrees C for 300 mi n, owing to a negligible local stress at the corner of the active and field region.