A continuous-time forward equalizer with one adaptive zero and a seventh-or
der linear-phase low-pass filter are described. The forward equalizer cance
ls precursor intersymbol interference (ISI), A mixed-signal four-tap RAM de
cision-feedback equalizer (DFE) is also included on the prototype to cancel
the postcursor ISI, Both precursor and postcursor ISI are canceled in the
analog domain. The adaption is done digitally. The low-pass filter and forw
ard equalizer together occupy 6.7 mm(2) in a 1-mu m CMOS process. They diss
ipate 280 mW from a 5-V supply when operating at 80 Mb/s. Including the RAM
-DFE, the entire chip occupies 11.2 mm(2) and dissipates 630 mW.