SymFony: A hybrid topological-symbolic ATPG exploiting RT-level information

Combining different techniques for sequential automated test pattern genera tion (ATPG) can help overcome their respective limits and exploit their adv antages. In this paper, a hybrid technique resulting from mixing topologic and symbolic approaches to the sequential ATPG problem is presented. Macros are first identified within the circuit (possibly resorting to RT-level kn owledge of circuit architecture). Information about macro behavior is then computed and efficiently stored resorting to symbolic techniques. A topolog ical tool exploits this information during the ATPG process to speed-up the propagation task and to identify early unsuccessful choices, Experimental results are reported, demonstrating that the method is able to improve the efficiency of a topological ATPG in terms of required CPU time and attained fault coverage, especially on medium-sized control-dominated circuits.