Accurate high-speed performance prediction for full differential current-mode logic: The effect of dielectric anisotropy

Integrated-circuit interconnect characterization is growing in importance a s devices become faster and smaller. Along with this trend, interconnect ge ometry is becoming more complex, consisting of an increasing number of wiri ng levels. Accurate numerical extraction of three-dimensional (3-D) interco nnect capacitance is essential for achieving design targets in the multigig ahertz digital regime. Interconnect-capacitance extraction is complicated b y the presence of inhomogeneous layers with differing dielectric constant. Dielectric anisotropy as well is common in many low-kappa polymeric dielect rics used in high-performance IC's. A CAD procedure using the novel floatin g random-walk extractor QuickCAP is presented. Our procedure is efficient e nough to extract a substantial amount of a chip's 3-D wiring. We include as well dielectric anisotropy and inhomogeneity. The procedure is not based o n effective conductor geometry or on a finite-sized conductor library but r ather on the entire 3-D layout, accounting for actual local variations in c onductor separations and shapes. We then apply our procedure to an experime ntal circuit vehicle implemented in AlGaAs/GaAs heterojunction bipolar tran sistor current-mode logic. This vehicle is used to validate the accuracy of our CAD procedure in predicting circuit speed. Measured and predicted test -capacitor values and ring-oscillator propagation times agreed generally to within 2-4%. To verify results on a larger digital circuit, we analyzed al l interconnects in an adder carry-chain oscillator using our procedure. Pre dicted propagation delays were generally within 3% of measurement.