The effect of webs and substrate type on gate oxide charging damage during
plasma processing, and more specifically plasma immersion ion implantation,
is modeled, The simulation combines the equations governing the plasma cur
rents and integrated circuit device models to determine the gate oxide stre
ssing voltage during implantation. Depending on the substrate type and the
surface potential (V-s), a depletion region may exist, reducing the gate ox
ide voltage, and hence the gate oxide damage, In addition, well structures,
by the nature of their capacitance, modulate V-s, altering the oxide stres
sing voltage. For most PIII implant conditions, gate oxides with p-type cha
nnel doping mill be damaged more than those oxides with n-type channel dopi
ng. Experimental results confirm the substrate and well effects on plasma c
harging damage.