Simulation of complete VLSI fabrication processes with heterogeneous simulation tools

Citation
Cm. Pichler et al., Simulation of complete VLSI fabrication processes with heterogeneous simulation tools, IEEE SEMIC, 12(1), 1999, pp. 76-86
Citations number
36
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING
ISSN journal
08946507 → ACNP
Volume
12
Issue
1
Year of publication
1999
Pages
76 - 86
Database
ISI
SICI code
0894-6507(199902)12:1<76:SOCVFP>2.0.ZU;2-7
Abstract
An integrated environment for the simulation of VLSI fabrication processes is presented. Emphasis is put on automated operation to achieve maximum eff iciency in TCAD deployment. Addressing the increasing number and diversity of process steps in state-of-the-art semiconductor fabrication processes, m echanisms have been devised to support the smooth, automatic interaction of heterogeneous simulation tools with multiple data formats in the context o f large-scale experiments for global calibration, device optimization, and yield improvement tasks. For maximum versatility, the operation of the envi ronment is either controlled via a graphical user interface, a batch file, or a combination of the two. It is possible to submit predefined analysis t asks for background execution, while still being able to monitor and contro l operation and to access and view simulation data interactively. Split-lot experiments are performed on workstation clusters in parallel operation, d elivering the desired results in the shortest possible time. The TCAD envir onment presented offers server functionality for running large number of co mplex simulations. At the same time, it supports the design and seamless in tegration into the environment of client task applications.