Modeling architectures for VLSI implementations of fuzzy logic systems

A model for predicting silicon area occupied by a fuzzy logic system implem ented in VLSI is presented. The model aims to allow designers to estimate t he feasibility of implementing their fuzzy logic system in hardware and sho uld also enable the identification of core-limited or interconnect-limited designs. A set of examples showing typical results are presented. These ill ustrate the dominant impact of interconnect on silicon area in hardware imp lementations of fuzzy logic systems. (C) 1999 Elsevier Science Inc. All rig hts reserved.