Flicker noise is investigated in a set of transistors issued from a 0.8 mu
m CMOS technology in order to extract parameters for simulation using BSIM3
(Berkeley Short-channel IGFET Model). The noise model used in BSIM3 is dis
cussed, an appropriate extraction procedure is proposed. Intrinsic channel
noise variations versus device biases agree with Hooge's theory (carrier mo
bility fluctuations) for p-MOSTs and with Me Whorter's theory (carrier numb
er fluctuations) for n-MOSTs. It is shown that for the studied technology t
wo noise parameters (NOIA and NOIB) can model the intrinsic channel noise.
For p-MOSTs, NOIA and NOIB are constants and for n-MOSTs NOIA is also a con
stant while NOIB is inversely proportional to the effective gate voltage. G
ood agreement between simulation and experimental results is obtained. (C)
1999 Elsevier Science Ltd. All rights reserved.