An efficient multistage switching node architecture for broadband ISDNs

This paper proposes and analyses a new and efficient multistage switching n ode architecture for high-speed communication networks such as Broadband In tegrated Services Digital Networks (BISDNs). The proposed architecture has several superior features as compared to the existing switching nodes based on Banyan architecture. The architecture uses a reduced number of stages i n an attempt to reduce the delay. Each switching element has its own input buffer and that reduces the blocking probability. Performance of the propos ed architecture has been evaluated using simulation. The performance result s are presented in the form of utilization, and delay, with different buffe r sizes. The results show that the proposed architecture provides better pe rformance in terms of reduced delay and higher throughput.