Transient self back-biased buffer for low-voltage high-performance applications in standard CMOS technologies

Authors
Moisiadis, Y Bouras, I Papadas, C Schoellkopf, JP
Citation
Y. Moisiadis et al., Transient self back-biased buffer for low-voltage high-performance applications in standard CMOS technologies, ELECTR LETT, 35(2), 1999, pp. 112-113
Citations number
4
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
ELECTRONICS LETTERS
ISSN journal
00135194 → ACNP
Volume
35
Issue
2
Year of publication
1999
Pages
112 - 113
Database
ISI
SICI code
0013-5194(19990121)35:2<112:TSBBFL>2.0.ZU;2-C
Abstract
A low-voltage, high performance buffer suitable for implementation in stand ard CMOS technologies is proposed. The new buffer utilises the transient se lf back-bias (TSBB) technique to reduce electrically the threshold voltage of the output PMOS transistor, enhancing its performance. Simulations at 10 0MHz and 0.9V have shown that the TSBB buffer has a 35% speed advantage in the pull-up over the standard CMOS buffer, with only 5% increase in power d issipation.