SIRENA: A CAD environment for behavioural modelling and simulation of VLSIcellular neural network chips

This paper presents SIRENA, a CAD environment for the simulation and modell ing of mixed-signal VLSI parallel processing chips based on cellular neural networks. SIRENA includes capabilities for: (a) the description of nominal and non-ideal operation of CNN analogue circuitry at the behavioural level ; (b) performing realistic simulations of the transient evolution of physic al CNNs including deviations due to second-order effects of the hardware; a nd, (c) evaluating sensitivity figures, and realize noise and Monte Carlo s imulations in the time domain. These capabilities portray SIRENA as better suited for CNN chip development than algorithmic simulation packages (such as OpenSimulator, Sesame) or conventional neural networks simulators (RCS, GENESIS, SFINX), which are not oriented to the evaluation of hardware non-i dealities. As compared to conventional electrical simulators (such as HSPIC E or ELDO-FAS), SIRENA provides easier modelling of the hardware parasitics , a significant reduction in computation time, and similar accuracy levels. Consequently, iteration during the design procedure becomes possible, supp orting decision making regarding design strategies and dimensioning. SIRENA has been developed using object-oriented programming techniques in C, and currently runs under the UNIX operating system and X-Windows framework. It employs a dedicated high-level hardware description language: DECEL, fitted to the description of non-idealities arising in CNN hardware. This languag e has been developed aiming generality, in the sense of making no restricti ons on the network models that can be implemented. SIRENA is highly modular and composed of independent tools. This simplifies future expansions and i mprovements, Copyright (C) 1999 John Wiley & Sons, Ltd.