The characteristics and performance of the resist flow process (RFP), which
is one of the contact hole (CM) shrinking technologies, were investigated
for sub-150 nm C/H patterns using KrF (lambda = 248 nm) lithography. A fine
C/H pattern was defined by adopting optimized process parameters at a high
er baking temperature than the glass transition temperature of the used mat
rix material. The shrinking limit of the C/H pattern was in the range of 40
-50 nm without any deformation in profile from the original C/H size, howev
er, the bowing profile of the C/H pattern was observed in the case of a shr
inking bias larger than 50 nm. It was also found that the amount of shrinka
ge of the C/H pattern was strongly dependent on the baking temperature, tot
al quantity of the resist surrounding the C/H pattern, and resist thickness
. When the 150 nm C/H pattern was formed by RFP from a 180 nm C/H generated
by an attenuated phase shifting mask (PSM), the depth of focus (DOF) and t
he energy latitude (EL) were 1.6 mu m and 16%, respectively, and the critic
al dimension (CD) uniformity in an 8-inch wafer was less than 25 nm. In thi
s study, in spite of baking to enable resist flow, the etch selectivity of
resist on silicon substrates was not changed and the C/H pattern on silicon
oxide after the etching process showed a vertical profile. Based on these
results, it is believed that the RFP for a sub-150 nm C/H pattern will be a
very promising candidate for the mass production of gigabit devices.