A nano-structure memory with silicon on insulator edge channel and a nano dot

Citation
G. Park et al., A nano-structure memory with silicon on insulator edge channel and a nano dot, JPN J A P 1, 37(12B), 1998, pp. 7190-7192
Citations number
8
Categorie Soggetti
Apllied Physucs/Condensed Matter/Materiales Science
Volume
37
Issue
12B
Year of publication
1998
Pages
7190 - 7192
Database
ISI
SICI code
Abstract
We fabricated nano structure memory with silicon on insulator (SOI) edge ch annel and a nano dot. The width of the edge channel was determined by the t hickness of the recessed rep-silicon layer of SOI wafer and the size of sid ewall nano dot was determined by the reactive ion etching (RIE) etch and E- beam lithography. The memory has the threshold voltage shift of about 1 V f or maximum programming voltage of 7 V and showed reasonable retention and e ndurance characteristics.