This paper discusses the implementation of the building blocks for a 2 GHz
phase-locked loop frequency synthesizer in a standard 0.5 mu m BICMOS proce
ss. These blocks include a low-power optimized dual modulus prescaler which
is able to operate with input frequencies up to 2.7 GHz, a phase detector
with extremely constant gain throughout the input phase difference range, a
chargepump with a rail-to-rail output, and an on-chip voltage-controlled o
scillator.