Power reduction in custom CMOS digital filter structures

Today the main optimization parameter of digital filters is the filter orde r. By the aid of two implemented filters we will show that both power and s peed can be enhanced if the optimization effort is made on reducing the fil ter coefficient lengths rather than minimizing the order. Both filters have been designed from the same specification, one as a standard minimum order filter, the other as a filter with short coefficients found by a computer search. The minimum order filter is of order three with seven bits long coe fficients, The coefficient optimized filter is of order six with two bits l ong coefficients. Both filters were implemented with bit-serial fixed coeff icient arithmetic in two's complement representation in a 0.8 mu, two metal layers CMOS process. Measurements show an eightfold speedup at half the po wer consumption and only 30% area cost for the coefficient optimized filter .