Modeling digital substrate noise injection in mixed-signal IC's

Techniques are presented to compactly represent substrate noise currents in jected by digital networks, Using device-level simulation, every gate in a given library is modeled by means of the signal waveform it injects into th e substrate, depending on its input transition scheme. For a given sequence of input rectors, the switching activity of every node in the Boolean netw ork is computed. Assuming that technology mapping has been performed, each node corresponds to a gate in the library, hence, to a specific injection w aveform. The noise contribution of each node is computed by convolving its switching activity with the associated injection waveforms. The total injec ted noise for the digital block is then obtained by summing all the noise c ontributions in the circuit. The resulting injected noise can be viewed as a random process, whose power spectrum is computed using standard signal pr ocessing techniques. A study was performed on a number of standard benchmar k circuits to verify the validity of the assumptions and to measure the acc uracy of the obtained power spectra.