Modelling output waveform and propagation delay of a CMOS inverter in the submicron range

An accurate, analytical model is presented for the evaluation of the CMOS i nverter delay in the submicron regime. Following an exhaustive analysis of the inverter operation. accurate expressions of the output response to an i nput ramp are derived, which result in the analytical calculation of the pr opagation delay. These expressions are valid for all the inverter operation regions and input waveform slopes, and take into account the influences of the short-circuit current and the gate-drain coupling capacitance. The eff ective output transition time of the inverter is determined, in order to ma p the real output waveform to a ramp waveform for the model to be applicabl e to CMOS gate chains. The results are in very good agreement with SPICE si mulations.