Packaging impact on switching noise in high-speed digital systems

Owing to the ever-increasing clock frequency in digital circuits and system s. simultaneous switching noise (SSN), caused by fast rise/fall pulse edges in combination with parasitic inductance in the power supply distribution network, is becoming a severe problem in many high-speed digital system des igns. It is quantitatively shown that the influence of SSN. which is neglig ible when the rise/fall time is long (> 5ns), becomes a critical factor, li miting system performance in the subnanosecond rise time region. Based on t heoretical analyses and computational simulations in respect to various pac kaging techniques. technical solutions and design guidelines for reducing S SN are summarised.