Segmented bus design for low-power systems

This paper(1) proposes a bus-segmentation method that efficiently reduces t he switched capacitance on the bus. The power consumed by the bus can, ther efore, be substantially reduced. The basic idea of bus segmentation is to p artition the bus into several bus segments separated by pass transistors. H ighly communicating devices are located to adjacent bus segments, thus, mos t data communication can be achieved by switching a small portion of the bu s segments. As a result, power consumption and critical path delay are both reduced. Experimental results obtained by simulating a delay model and a p ower model demonstrate that the proposed segmented bus system reduces bus p ower by about 60%-70% and improves critical bus delay by about 10%-30%.