An efficient VLSI architecture for 2-D wavelet image coding with novel image scan

A folded very large scale integration (VLSI) architecture is presented for the implementation of the two-dimensional discrete wavelet transform, witho ut constraints on the choice of the wavelet filter bank, The proposed archi tecture is dedicated to flexible block oriented image processing, such as a daptive vector quantization used in wavelet image coding. We show that read ing the image along a two-dimensional (2-D) pseudo-fractal scan creates a v ery modular and regular data flow and, therefore, considerably reduces the folding complexity and memory requirements for VLSI implementation, This le ads to significant area savings for on-chip storage (up to a factor of two) and reduces the power consumption. Furthermore, data scheduling and memory management remain very simple. The end result is an efficient VLSI impleme ntation with a reduced area cost compared to the conventional approaches, r eading the input data Line by Line.