High performance low power away multiplier using temporal tiling

Digital multipliers are a major source power dissipation in digital signal processors. Array architecture is a popular technique to implement these mu ltipliers due to its regular compact structure. High power dissipation in t hese structures is mainly due to the switching of a large number of gates d uring multiplication. In addition, much power is also dissipated due to a l arge number of spurious transitions on internal nodes. Timing analysis of a full adder, which is a basic building block in array multipliers, has resu lted in a different array connection pattern that reduces power dissipation due to the spurious transition activity. Furthermore, this connection patt ern also improves the multiplier throughput. This array pattern is based on creating a compact tiled structure, wherein the shape of a tile represents the delay through that tile. That is, a compact structure created using th ese tiles is nothing but a structure with high throughput. Such a temporal tiling technique can also he applied to other digital circuits. Based on ou r simulation studies, a temporally tiled array multiplier achieves 50% and 35% improvements in delay and power dissipation compared to a conventional array multiplier. Improvement in delay can be traded for power using voltag e reduction techniques.