Performance enhancement on digital signal processors with complex arithmetic capability

Citation
Y. Negishi et al., Performance enhancement on digital signal processors with complex arithmetic capability, IEICE T FUN, E82A(2), 1999, pp. 238-245
Citations number
14
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES
ISSN journal
09168508 → ACNP
Volume
E82A
Issue
2
Year of publication
1999
Pages
238 - 245
Database
ISI
SICI code
0916-8508(199902)E82A:2<238:PEODSP>2.0.ZU;2-#
Abstract
Digital Signal Processors with complex arithmetic capability (DSP-C) are us eful for various applications. In this paper, we propose a method for the e ffective implementation of specific circuits with real coefficients on DSP- C. DSP-C has special hardware such as a complex multiplier so that a comple x calculation can be performed with only one instruction. First, we show th at nodes with two real coefficient input branches can be implemented by com plex multiplications. We apply this implementation to 2D circuits and trans versal circuits with real coefficients. Next, we introduce a new computatio nal mode (Advanced mode) and a new multiplier into PSI, a kind of DSP-C whi ch has been proposed already, in order to process the circuits effectively. The effectiveness of the proposed method is shown by simulation in the las t part.