A CMOS analog multiplier free from mobility reduction and body effect

This paper proposes a novel CMOS analog multiplier. As its significant meri t, it is free from mobility reduction and body effect. Thus, the proposed m ultiplier is expected to have good linearity, comparing with conventional m ultipliers. Four transistors operating in the linear region constitute the input cell of the multiplier. Their sources and backgates are connected to the ground to cancel the body effect. Their gates are fixed to the same bia s voltage to remove the effect of the mobility reduction. Input signals are applied to the drains of the input cell transistors through modified nullo rs. The simulation results show that THD is less than 0.8% for 0.6 Vp-p inp ut signal at 2.5-V supply voltage, and that the 3-dB bandwidth is up to abo ut 13.3 MHz.