Layout dependent matching analysis of CMOS circuits

Layout has strong influence on matching properties of a circuit. Current ma tching models, which characterize both local random non-uniformities and gl obal systematic nonuniformities stochastically, are not adequate for the ma tching analysis taking the effect of layout realization into account. In or der to consider topological information of layout into matching analysis, w e propose a matching model which treats the random and systematic component s separately. Also, we characterize the micro-loading effect, which modulat es fabricated line-width according to the local density of layout patterns, into matching analysis. With these two techniques, we can perform matching analysis of CMOS circuits taking layout information into account.