An analog-digital merged neural circuit using pulse width modulation technique

This paper presents a neural circuit using PWM technique based on an analog -digital merged circuit architecture. Some new PWM circuit techniques are p roposed. A bipolar-weighted summation circuit is described which attains 8- bit precision in SPICE simulation at 5V supply voltage by compensating para sitic capacitance effects. A high performance differential-type latch compa rator which can discriminate 1 mV difference at 100 MHz in SPICE simulation is also described. Next, we present a prototype chip fabricated using a 0. 6 mu m CMOS process. The measurement results demonstrate that the overall p recision in the weighted summation and the sigmoidal transformation is 5 bi ts. A neural network has been constructed using the prototype chips, and th e experimental results for realizing the XOR function have successfully ver ified the basic neural operation.