An all-implanted p-channel Si JFET fully compatible with CMOS technology

In this article, we show that a p-channel silicon Junction Field Effect Tra nsistor (JFET) can be obtained within a conventional CMOS n-well technology with no additional process steps but a simple layout modification of the p -channel-stop mask; in fact, in the suggested technology, the p-channel of the JFET is obtained by using the same CMOS p-stop implantation step. Resul ts from the electrical characterization of a specially designed test-chip c onfirmed the validity of the device concept and its full compatibility with CMOS devices; in particular, JFETs exhibit high transconductance and outpu t resistance as well as low gate current and input capacitance. The propose d technological approach has therefore proved to be suitable for the realiz ation of p-JFET-CMOS low-noise circuits. (C) 1999 Elsevier Science Ltd. All rights reserved.