Single-gate 0.15 and 0.12 mu m CMOS with Co salicide technology

Authors
Yoshitomi, T Saito, M Ohguro, T Ono, M Momose, HS Morifuji, E Morimoto, T Katsumata, Y Iwai, H
Citation
T. Yoshitomi et al., Single-gate 0.15 and 0.12 mu m CMOS with Co salicide technology, SOL ST ELEC, 43(3), 1999, pp. 543-546
Citations number
7
Categorie Soggetti
Apllied Physucs/Condensed Matter/Materiales Science","Eletrical & Eletronics Engineeing
Journal title
SOLID-STATE ELECTRONICS
ISSN journal
00381101 → ACNP
Volume
43
Issue
3
Year of publication
1999
Pages
543 - 546
Database
ISI
SICI code
0038-1101(199903)43:3<543:S0A0MM>2.0.ZU;2-I
Abstract
A high-speed 0.15 mu m single-gate Co salicide CMOS technology has been dem onstrated, which suppresses short channel effects in 0.15 mu m buried chann el pMOSFETs by optimizing the fabrication conditions of their extension reg ion. An unloaded CMOS inverter ring-oscillator delay of 19.8 ps has been ob tained. At 0.12 mu m gate length, 11.4 ps gate delay was observed. (C) 1999 Elsevier Science Ltd. All rights reserved.