Buried p-gate heterojunction field effect transistor

Citation
M. Nakamura et al., Buried p-gate heterojunction field effect transistor, ELECTR LETT, 35(4), 1999, pp. 336-338
Citations number
4
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
ELECTRONICS LETTERS
ISSN journal
00135194 → ACNP
Volume
35
Issue
4
Year of publication
1999
Pages
336 - 338
Database
ISI
SICI code
0013-5194(19990218)35:4<336:BPHFET>2.0.ZU;2-Z
Abstract
A buried p(+)-AlGaAs gate AlGaAs/InGaAs/AlGaAs double heterostructure field effect transistor (FET) (p-gate HFET) operating in enhancement mode has be en successfully fabricated using the Zn-diffusion technique. A low on-resis tance of 1.6 Ohm mm and a high gate built-in voltage of 1.5V with a maximum transconductance of 420mS/mm were obtained for a 0.8 mu m gate device. The buried p-gate HFET is promising for power-FET applications which require l ow distortion, high efficiency and positive bias operation.