Plasma-etching processes for ULSI semiconductor circuits

An overview is presented of plasma-etching processes used in the fabricatio n of ULSI (ultralarge-scale integrated) semiconductor circuits, with emphas is on work in our facilities. Such circuits contain structures having minim um pattern widths of 0.25 mu m and less. Challenges in plasma etching in ev olving to such dimensions have come from the implementation of antireflecti ve coatings and thinner, more etch-sensitive photoresists; the increased as pect ratios needed to meet design requirements; the additional hard-mask et ching steps needed at levels at which lithography is unsuitable for pattern ing; and increased selectivity requirements, such as the requirement that c ontact structures be self-aligning. Future circuit density and performance requirements dictate tighter specifications for linewidth variations permit ted across a wafer, microloading effects, and device damage. As a result, p lasma-etching systems for critical levels are migrating from traditional mu ltifilm, capacitively coupled low-density-plasma systems to medium- and hig h-density-plasma systems employing exotic or highly polymerizing chemical s pecies specifically designed for one type of film.