PTM: Technology mapper for pass-transistor logic

The pass-transistor mapper (PTM) is reported; this is a logic synthesis too l specifically designed for pass-transistor-based logic library that has on ly three basic cells. It exploits the close relationship between a binary d ecision diagram (BDD) representation of logic and the structure of pass-tra nsistor logic cells to ensure efficient technology mapping. BDD-variable or der optimisation is achieved through a genetic algorithm with dynamic param eters. Unlike a previous system for pass-transistor logic, PTM integrates b oth synthesis and logic optimisation in one step and can be used for large logic functions. Results from using PTM on a large set of benchmarks are an alysed using the MCNC CMOS cell library and are found to be promising.