In this paper, a timing-driven genetic placer for standard-cell IC design i
s presented. The objective of the placer comprises minimizing both area and
path delays. The objective function is such that when the algorithm starts
converging toward generations with acceptable delay properties, the object
ive is dynamically adjusted toward optimizing area and wire length. Experim
ents with benchmark tests demonstrate delay performance improvement by up t
o 20%. It is also shown that sizable reduction in runtime is obtained when
population size is allowed to decrease in a controlled manner whenever the
search hits a plateau. This reduction in runtime is achieved without any no
ticeable loss in solution quality.