A novel CMOS low-voltage output stage is proposed. It is based on a class A
B common source configuration with improved efficiency in terms of drive ca
pability compared with silicon area. It provides a drive capability which i
s greater than the previous solution by a factor of 2 with the same aspect
ratios and the same quiescent current. A 2mA peak-to-peak output current is
achieved with a 1.2 mu m CMOS process, a 1.2V power supply and a maximum o
utput transistor aspect ratio of 375/1.2. The output stage is also well con
trolled under bias conditions, and hence standby power dissipation, frequen
cy response and small signal linearity are all well defined.