2.5 Gbit/s clock and data recovery circuit IC using novel duplicated PLL technique

A 2.5Gbit/s monolithic clock and data recovery integrated circuit (CDR IC) based on a novel duplicated phase-locked loop (PLL) technique has been fabr icated using 0.5 mu m Si bipolar technology. This CDR IC operates more stab ly in that it can tolerate greater variations in temperature and supply vol tage while continuing to meet the specifications for jitter characteristics stipulated in the ITU-T recommendations.