The multiplication, inversion, division and exponentiation of elements of G
F(2(m)) are easily implemented with conventional arithmetic and logical uni
ts when the elements are in the logarithmic representation. An electronic a
rchitecture for the addition of two elements in the logarithmic representat
ion is presented. The architecture of the adder is similar to that of the M
assey-Omura multiplier for the normal basis representation. In particular,
the same combinatorial circuit is used to successively compute every bit of
the sum.