ANNSyS: an Analog Neural Network Synthesis System

A synthesis system based on a circuit simulator and a silicon assembler for analog neural networks to be implemented in MOS technology is presented. T he system approximates on-chip training of the neural network under conside ration and provides the best starting point for 'chip-in-the-loop training' . Behaviour of the analogs neural network circuitry is modeled according to its SPICE simulations and those models are used in the initial training of the analog neural networks prior to the fine tuning stage. In this stage, the simulator has been combined with Madaline Rule III for approximating on chip training by software, thus minimizing the effects of circuit nonideal ities on neural networks. The circuit simulator partitions the circuit into decoupled blocks which can be simulated separately, with the output of one block being the input for the next one. Finally, the silicon assembler gen erates the layout for the neural network by reading analog standard cells f rom a library, The system's performance has been demonstrated by several ex amples. (C) 1999 Elsevier Science Ltd. All rights reserved.