Graphical approach for multiple valued logic minimization

Multiple valued logic (MVL) is sought for designing high complexity, highly compact, parallel digital circuits. However, the practical realization of an MVL-based system is dependent on optimization of cost, which directly af fects the optical setup. We propose a minimization technique for MVL logic optimization based on graphical visualization, such as a Karnaugh map. The proposed method is utilized to solve signed-digit binary and trinary logic minimization problems. The usefulness of the minimization technique is demo nstrated for the optical implementation of MVL circuits. (C) 1999 Society o f Photo-Optical Instrumentation Engineers. [S0091-3286(99)01103-4].