A timing-driven soft-macro placement and resynthesis method in interactionwith chip floorplanning

In this paper, we present a complete chip design method which incorporates a soft-macro placement and resynthesis method in interaction with chip floo rplanning for area and timing improvements. We present a performance-driven soft-macro clustering and placement method which preserves hardware descri ptive language (HDL) design hierarchy to guide the soft-macro placement pro cess. We develop a timing-driven design flow to exploit the interaction bet ween HDL synthesis and physical design tasks. During each design iteration, we resynthesize soft macros with either a relaxed or a tightened timing co nstraint which is guided by the post-layout timing information. The goal is to produce area-efficient designs while satisfying the timing constraints. Experiments on a number of industrial designs ranging from 75-K to 230-K g ates demonstrate that the proposed soft-macro clustering and placement meth od improves critical-path delays on an average of 22%, Furthermore, the res ults show that by effectively relaxing the timing constraint of noncritical modules and tightening the timing constraint of critical modules, a design can achieve 11% to 30% timing improvements with little to no increase in c hip area.