Fast static compaction algorithms for sequential circuit test vectors

Two fast algorithms for static test sequence compaction are proposed for se quential circuits. The algorithms are based on the observation that test se quences traverse through a small set of states and some states are frequent ly revisited throughout the application of a test set. Subsequences that st art and end on the same states may be removed if necessary and if sufficien t conditions are met for them. Contrary to the previously proposed methods, where multitudes of fault simulations are required, the techniques describ ed in this paper require only two fault simulation passes and are applied t o test sequences generated by various test generators, resulting in signifi cant compactions very quickly for circuits that have many revisited states.