Efficient techniques for dynamic test sequence compaction

Dynamic test sequence compaction is an effective means of reducing test app lication time and often results in higher fault coverages and reduced test generation time as well. Three simulation-based techniques for dynamic comp action of test sequences are described. The first technique uses a fault si mulator to remove test vectors from the test sequence generated by a test g enerator if the vectors are not needed to detect the target fault, consider ing that the circuit state may be known. The second technique uses genetic algorithms to fill the unspecified bits in a partially-specified test seque nce in order to increase the number of faults detected by the sequence. The third technique uses test sequences provided by the test generator as seed s in a genetic algorithm, and better sequences are evolved that detect more faults. Significant improvements in test set size, fault coverage, and tes t generation time have been obtained over previous approaches using combina tions of the three techniques.