Single-electron memory for giga-to-tera bit storage

Starting with a brief review on the single-electron memory and its signific ance among various single-electron devices, this paper addresses the key is sues which one inevitably encounters when one tries to achieve giga-to-tera bit memory integration. Among the issues discussed are: room-temperature o peration; memory-cell architecture; sensing scheme; cell-design guideline; use of nanocrystalline silicon versus lithography; array architecture ; dev ice-to-device variations; read/write error rate; and CMOS/single-electron-m emory hybrid integration and its positioning among various memory architect ures.