Wj. Chen et Ws. Feng, PATTERN-BASED MAXIMAL POWER ESTIMATION FOR VLSI CHIP DESIGN, IEICE transactions on fundamentals of electronics, communications and computer science, E80A(11), 1997, pp. 2300-2307
In recently year, the analysis of power management becomes more import
ant. It is difficult to obtain the maximum power because this is NP-co
mplete. For an n-input circuit, there are 2(2n) different input patter
ns to be considered. There are two major methods for this problem. Fir
st method is to generate input patterns to obtain the maximal power by
simulating these generated patterns. This method is called pattern ba
sed. The other one uses probability method to estimate the power densi
ty of each node of a circuit to calculate the maximal power. In this p
aper, we use a pattern based method to estimate the maximal power. Thi
s method is better than that of probability for the simulation of powe
r activity. In practical applications, these generated patterns can be
applied and observe the activity of a circuit. These simulated data c
an be used to examined the critical paths for performance optimization
. A simulated annealing algorithm is proposed to search input patterns
for maximum power. Firstly, it transforms this problem into an optimi
zation problem to adapt the simulated annealing method. In this method
, there are three strategies for generating the next input patterns, c
alled neighborhood. In the first strategy, it generates the next input
pattern by changing the status of all input nodes. In the second stra
tegy, some input nodes are selected and changed randomly. In the last
strategy, it separates the input nodes into many groups and then selec
ts one, randomly, to change its status. These different strategies hav
e different solution space for the same input space. They will improve
the searching speed and the accurate result. When a new result is acc
epted we use a Walk-Through method to search the local optimal result.
To analyze the cost function in simulated annealing, a power dissipat
ion model is proposed including the glitch phenomena, fanout load, and
circuit type. For the criterion of equilibrium condition of annealing
temperature, we use a statistical model to estimate the optimal itera
tion number in a temperature.