AN AREA-EFFICIENT PIPELINED VLSI ARCHITECTURE FOR DECODING OF REED-SOLOMON CODES BASED ON A TIME-DOMAIN ALGORITHM

Reed-Solomon (RS) codes have been widely used in a variety of communic ation systems to protect digital data against errors occurring in the transmission process. Since the decoding profess for RS codes is rathe r computation-extensive, special-purpose hardware structures are often necessary for it to meet the real-time requirements. In this paper, a n area-efficient pipelined very large scale integration (VLSI) archite cture is proposed for RS decoding. The architecture is developed based on a time-domain algorithm using the remainder decoding concept. A pr ominent feature of the proposed system is that, for a t-error-correcti ng RS code with block length n, it involves only 2t consecutive symbol s to compute a discrepancy value in the decoding process, instead of n consecutive symbols used in the previous RS decoders based on the sam e algorithm without using the remainder decoding concept. The proposed RS decoder can process one data block every n clerk cycles, i.e., the average decoding rate is one symbol per clock cycle. As compared to a similar pipelined RS decoder with the same decoding rate, it gains si gnificant improvements in hardware complexity and latency.