G. Gratta et al., A FAST PROGRAMMABLE TRIGGER FOR PATTERN-RECOGNITION, Nuclear instruments & methods in physics research. Section A, Accelerators, spectrometers, detectors and associated equipment, 400(2-3), 1997, pp. 456-462
We have built a fast programmable trigger processor based on a state-o
f-the-art Field Programmable Gate Array (FPGA) IC for the Pale Verde N
eutrino Oscillation Experiment. The trigger processor can accommodate
160 ECL input signals, 8 NIM input signals, 16 ECL output signals and
8 NLM output signals. Our two-level trigger logic is designed asynchro
nously to maximize speed. We have attained trigger times of 40 ns for
level 1 and 100 ns far level 2 with 132 asynchronous inputs. The trigg
er processor can be upgraded by replacing the FPGA with more advanced
versions of tile chip as they appear.