STRUCTURE OF THE WAFER FUSED INP(001)-GAAS(001) INTERFACE

A structural study of wafer fused InP-GaAs interfaces has been carried out. The geometry of the dislocation network which accommodates the t wist and the lattice mismatch is first given using a geometrical appro ach. Cross-sectional transmission electron microscopy and plan view ob servations are presented. Two different misfit cases are observed. (1) When no twist is present, the 3.7% lattice mismatch is relaxed by a r egular square network of dislocations with pure edge character. (2) Wh en an additional twist is present, a square network of dislocations re sults as well but here the dislocations have a mixed character; 60 deg rees dislocations are also observed, some form closed defect circuits and others very likely accommodate a small tilt. The interaction betwe en the 60 degrees dislocations and the edge dislocations is explained in detail. Voids or inclusions are also observed as well as additional dislocations which may accommodate part of the thermal mismatch.