A 15-B, 5-MSAMPLE S LOW-SPURIOUS CMOS ADC

A 5-5-5-6-b pipelined analog-to-digital converter (ADC) architecture a lleviates the requirements for initial capacitor matching and residue amplifier settling accuracy, The two 5-b most significant bit (MSB) st ages are digitally calibrated to implement a 15-b, 5-Msample/s low-spu rious ADC using 1.4-mu m CMOS, A skip-and-fill algorithm with nonlinea r interpolation also opens up the possibility of calibrating ADC's in the background synchronously with their normal operation, Interpolatio n results for the background calibration are compared with the foregro und calibration results, The prototype ADC exhibits a differential non linearity (DNL) of +0.75/-0.6 least significant bit (LSB), an integral nonlinearity (INL) of +1.77/-1.58 LSB, and all spurious components ar e suppressed to below -93 dB when sampled at 5 MHz, The chip occupies 27 mm(2), and the analog part consumes 60 mW at 5 V, Memory and arithm etic units for calibration are supplied externally in testing.