COST-EFFECTIVE VLSI ARCHITECTURES FOR FULL-SEARCH BLOCK-MATCHING MOTION ESTIMATION ALGORITHM

In this paper, we present efficient VLSI architectures for full-search block-matching motion estimation (BMME) algorithm. Given a search ran ge, we partition it into sub-search arrays called tiles. By fully expl oiting data dependency within a tile, efficient VLSI architectures can be obtained. Using the proposed VLSI architectures, all the block-mat chings in a tile can be processed in parallel. All the tiles within a search range can be processed serially or concurrently depending on va rious requirements. With the consideration of processing speed, hardwa re cost, and I/O bandwidth, the optimal tile size for a specific video application is analyzed. By partitioning a search range into tiles wi th appropriate size, flexible VLSI designs with different throughput c an be obtained. In this way, cost effective VLSI designs for a wide ra nge of video applications, from H.261 to HDTV, can be achieved.